x86.lol
npub1txzkunpu5pvwhzjq96rs0l3amnx27gxx4swdzmk3rfg30lmrk0fsrrxa2w@drss.io
I'm blogging about low-level topics and my operating system projects on x86 and RISC-V.
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Polyglot NixOS: The Same Disk Image for All Architectures
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19 Dec 2025
Recently a [colleague](https://github.com/samueldr) mentioned building NixOS images that run unchanged on multiple architectures. Given the past adventures on this blog with
Quick and Dirty Website Change Monitoring
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10 Aug 2025
Let’s say, you need to monitor a website for changes and you really don’t have a lot of time to set things up. Also solving the problem with money using services, such as
FOSDEM Edition: Thoughts on the Microkernels
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30 Jan 2025
It’s [FOSDEM](https://fosdem.org/2025/) time! I have fond memories of the [Microkernel and Component-based OS devroom](https://fosdem.org/2025/schedule/track/microkernel/) in particular. It’s a
Hardening C Against ROP: Getting CET Shadow Stacks Working
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23 Sep 2024
This post shows you how to use [CET](https://www.intel.com/content/www/us/en/developer/articles/technical/technical-look-control-flow-enforcement-technology.html) [user shadow
Immutable Systems: Cross-Compiling for RISC-V using Nix Flakes
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21 Sep 2024
In my [last post](/generic/2024/08/28/systemd-sysupdate.html), we built whole disk images for embedded systems using [Nix](https://nixos.org). This approach is well suited for RISC-V or ARM systems,
Immutable Systems: NixOS + systemd-repart + systemd-sysupdate
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28 Aug 2024
When you build software for embedded devices (your Wi-Fi router or home automation setup on your Raspberry Pi), there is always the question how to build these images and how to update them. What I
Confidential Computing: Complexity vs Security
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7 Jul 2024
This blog post is a continuation of my [previous](/generic/2023/02/07/intel-tdx.html) [posts](/generic/2023/06/28/intel-tdx-2.html) about [Confidential
RISC-V: The (Almost) Unused Bit in JALR
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20 Dec 2023
In the [RISC-V](https://en.wikipedia.org/wiki/RISC-V) architecture, you have excellent support for embedding information into code by choosing compressed or uncompressed instructions. While being a
